Electronic engineers of Good future company are experienced in all phases of various designs from basic analog and digital circuits to RF and the latest wireless technology.
RFID Chip Descriptions
The CRONOS is a CMOS integrated circuit intended for use in contactless Read/Write transponders. It has passive and semi-passive operation modes. The configurable 64 bytes EEPROM memory contained in the chip is organized in 32 words of 16 bits for ID and user applications. The CRONOS110 has a built-in anti-collision protocol which allows an unlimited number of transponders in the reader field to communicate simultaneously.
- ISO 18000-4 part 1 (2.45 GHz) and ISO 18000-6 type B (UHF) compliant
- Passive and semi-passive modes
- Support for Multiple Tags (Anti-collision)
- Block write protection
- 48 bytes user memory
- Small die size (~2 mm2)
- Long read range operation (semi-passive)
- Frequency independent: Typically used at UHF and 2.45 GHz
- Low voltage operation – down to 1.5 V
- Stand-by mode with field sniffing (semi-passive)
- Very low power CMOS design
- Cost effective
- Access control
- Asset Management
- Supply chain management
- Traffic management
- Toll collection
The RFID chip is a silicon-proven IP available on 0.18 µm CMOS process.
Over the past decade we have done many other designs in various fields mostly in communication, RF and analog designs. We have a proven record in chip design. Below shows some of the designs we have delivered to customers:
- Multi System GNSS Receiver
- Advanced Double Conversion Radio Receiver
- UWB Transceiver Tag Plus Reader
- Wireless LAN 802.11b IC
- Wireless LAN 802.11a IC
- Fiber optic 10 Gbps Post Amplifier IC
- Fiber optic 10 Gbps Transimpedance Amplifier IC
- Fiber optic 10 Gbps Laser Diode Driver
- IF section of GSM transceiver chipset
- PHS phone receiver chipset
- DECT handset chipset and module
- Digital AMPS Mobile receiver chipset
- 1V CMOS Pager chipset
Our flexible silicon-proven IP solutions provide significant advances in cost reduction and power saving for several applications and consumer electronics industries.
Global Positioning System ( GPS )
The Good future GPS is a very low power consumption, low noise figure, high sensitivity, small in size, high performance and highly integrated architecture which is optimized for mainstream Position Location Services (PLS) and any application that requires low power consumption and very small sizes.
The Good future GPS-RF chip is based on 0.18 µm CMOS process technology. The device implements a Low-IF, single-conversion architecture that results in reduced external component count when compared to super-heterodyne architectures.
The Good future GPS-RF is available in a space-saving 48-pin TQFP package and is specified for the extended (-40°C to +85°C) temperature range.
This chip is designed to operate 1.8 volt power supplies.
The Good future GPS-BB is a 12-channel, multiplexed parallel GPS Baseband Signal Processor implemented in an FPGA & ARM processor. It is designed to receive a 1-bit-digitized 16f0 sampled 4f0 IF output of the Front-End chip.
The Good future GPS-BB despreads & demodulates the 50 bps data stream embedded in the GPS signal and provides the estimated signal propagation and delays. Full position-velocity-time solution is then calculated.
The Good future RFID chip is an ISO 18000 compliant UHF/Microwave RFID transponder chip. The RFID chip has both passive and semi-passive modes of operation. It complies with the ISO 18000-4 part 1 standard for operation in 2.45 GHz as well as ISO 18000-6B for UHF operation. The chip has the advantage of low power consumption and has been implemented in a low cost 0.18 µm CMOS process.